"JIEP Advanced Electronics Packaging(JISSO) Technology Symposium"
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| Sponsored by:JIEP-Japan Institute of Electronics Packaging |
| Managed by:JPCA-Japan Electronics Packaging and Circuit Association |
| Period:Wed.,30 (Wed) - Fri., June 1 (3 days) |
| Place:TOKYO BIG SIGHT,Conference Tower 1F,Room 101E102 |
| Registration
for "JIEP Advanced Electronics Packaging(JISSO) Technology Symposium" |
| Please click here. Registration |
| As soon as it becomes capacity, a reservation for the seat is shut. |
| There is a case that the contents of the instructor, program become changes by the reason. |
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Wed.,May 30
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Room A 101
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30A1
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 3D Packaging
Innovation 1 (Chip Level Stack Technology) |
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10:00-13:00
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Chariman:Haruo Tabata
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3D
Packaging Technology for Chip Stacked DRAM
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Toshiro Mitsuhashi,Manager,SIP Engineering Department,ATP
Manufacturing Division, |
Oki Electric Industry Co., Ltd. |
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The Advanced Approach
for SiP Technologies
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Michitaka Kimura,Jisso Technology
Development Dept.,Renesas Technology Corp. |
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Thinning
and Dicing Technologies for SiP
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Akihito Kawai,Marketing Team Leader,PS
Company Sales Engineering Department, |
DISCO CORPORATION |
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30A2
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3D
Packaging Innovation 2 (Packaging Level Stack Technology) |
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14:00-17:00
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Chariman:Hiroyuki Tenmei
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Reliable
PoP Jisso Realized by Machine and Process Evolution
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Takeshi Morita,Electronic
Component Mounting Systems & Solution Business Unit, |
Panasonic Factory Solutions Co., Ltd. |
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Current
Status & Future Technology for POP Assembly & Jisso
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Jun Taniguchi,Manager,3D CSP Product,Amkor
Technology Japan KK. |
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3D Packaging
- PoP Current Status and Future
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Takafumi Ando,Hiji Package Engineering,Texas
Instruments Japan |
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Room B 102
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30B1
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The Most
Advanced Estimation and CAE Technologies for High-speed Circuit Design |
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10:00-13:00
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CharimanFMitsubishi Electric Corp. Masahiro
Fukino
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| On-Chip Noise Measurements and Evaluation in SoCs | |
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Makoto Nagata,Assistant Professor,Department
of Computer and Systems Engineering, |
Kobe University |
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High Speed
Signal Propagation Design for Gigabit Transmission
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Ichiro Kambayashi,Application Engineering
Division,Tektronix Japan Ltd. |
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SI/PI
Solution for High-Speed Printed Circuit Board
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Masaki Tosaka,Corporate Technology
Unit,Corporate Circuit Technology Center, |
FUJITSU LIMITED |
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30B2
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JAPAN Jisso (Packaging Technology) Innovation (English Session) |
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14:00-17:00
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Chariman:Hiroshi Haji, Seiichi Denda
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| ¡Advanced PWB Technology Roadmap | |
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Mr. Henry H. Utsunomiya,President,Interconnection
Technologies, Inc. |
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Thin Wafer and Through Silicon Via
Technologies |
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Dr. Sei-ichi Denda,Visiting Professor,Nagano
Prefectural Institute of Technology, |
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¡System Integration Platform Organization
Standards (SIPOS) |
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Prof. Hajime Tomokage,Professor Dept.
of Electronics Engr. & Computer Sci., |
Fukuoka University |
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Thur.,May 31
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Room A 101
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31A1
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Novel
FPC technologies for Innovating Digital Mobile Equipments |
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10:00-13:00
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Chairman:Motoyo Wajima
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| Development of Brand-new Concept Multi Layer FPC by Using New Build Up Technology | |
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Garo Miyamoto,Research & Development,NIPPON MEKTRON,
LTD. |
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Technical
Trend of FPC Materials for Flex-rigid
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Hiroaki Takahashi,Flexible Circuit
Material Business Group, |
Electronic & Plastic Materials Company,Matsushita
Electric Works, Ltd. |
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Multi-Layer
FPC "Sbic" by Simultaneous Laminating Method and the Applied
Technology
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Masayoshi Kondo,Flexible Circuit Research & Development Dept., |
| Akita Sumitomo Bakelite Co., Ltd. | |
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31A2
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Come
into Practical Use PCBs with Embedded Components!- The Latest Status of Their Technology |
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14:00-17:00
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Chairman:Koji Ikawa
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| Development of Embedded Components Module Technology | |
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Masashi Miyazaki,Manager,EOMIN Project,Module Product Division,TAIYO YUDEN Co., LTD. |
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3D
Embedded Components Module Technology -SIMPACT-
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Yukihiro Ishimaru,Staff Engineer,Jisso Core Engineering Laboratory |
| ,Corporate Manufacturing Innovation Division,Matsushita Electric Industrial Co., Ltd. | |
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Application
to Module Technology of Build-up PWB Embedded Passive and Active
Devices
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Keisuke Okada,Executive Officer,Engineering and Development Department, |
| NEC TOPPAN CIRCUIT SOLUTIONS, INC. | |
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Room B 102
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31B1
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MEMS
Packaging,One of the
Most Important Factors in
Developing MEMS Products |
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10:00-13:00
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Chairman;Renshi Sawada
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| Silicon Tthrough Interconnection for MEMS Packaging | |
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Satoru Kuramochi,General Manager,Research and Development Center, |
| Dai Nippon Printing Co, Ltd. | |
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The Development of
MEMS-VOA
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Keiji Isamoto,Manager,Optical Component Design Group,Santec Corporation |
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¡Innovative
Process Technology for MEMS Wafer-level Packaging
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Takashi Saijo,EMIT Device Development Department,Process Development Group, |
| Matsushita Electric Works, Ltd. | |
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31B2
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Technology
Challenge in Optical Interconnecion |
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14:00-17:00
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Chairman:Kazuhiko Kurata
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| CIST and Photonic Functional Device Manufacturing Project | |
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Soichi Kobayashi,Professor,Department of Photonic Science, |
| Chitose Institute of Science and Technology | |
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Recent Oversea
R & D Progress in Optoelectronic Packaging Technology
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Takashi Mikawa,Opto-Electronic System Integration Collaborative Research Team,Nanoelectronics Research Institute,National Institute of Advanced Industrial Science |
| and Technology (AIST) | |
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Optical
Interconnect Technologies for Computing Systems
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Shigeru Nakagawa,Advisory Researcher,IBM Japan Tokyo Research Laboratory |
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Fri.,June 1
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Room A 101
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01A1
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High Efficiency Heat Transfer Technology that Holds the Key of Electronic Device Performance |
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10:00-13:00
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Chairman:Satoshi Yanaura
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| Thermal Management of Fujitsu High-End Unix Servers | |
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Jie Wei,Corporate Technology Center,Corporate Product Technology Unit,FUJITSU LIMITED |
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Technical Trend of High Thermal-conductive Insulated Metal Substrate
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Naomi Yonemura,Technical Sales Manager,Electronic Materials Business Division, |
| Denki Kagaku Kogyo Kabusikikaisha | |
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Micro-channel Heat Sink
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Tetsuro Ogushi,Principal Researcher,Mechanical Technology Dept.,Advanced Technology |
| R&D Center,Mitsubishi Electric Corporation | |
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Room B 102
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01B1
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Printable Electronics in Advanced Stage |
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10:00-13:00
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Chairman:Shigeru Kohinata
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| Printable Electronics by Inkjet Technology for Nano Metal Dispersed Ink | |
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Shinichi Nishi,R&D General Manager,Konicaminolta IJ Technologies, Inc |
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Challenge to Prepare Fine Electronic Circuit Pattern by the Use of Copper Nanoparticle Paste
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Masami Nakamoto,Manager,Organic Materials Department, |
| Osaka Municipal Technical Research Institute | |
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Inkjet Technology for Jisso Applications
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Kenji Wada,General Manager,IJ Industrial Applications R&D Dept.,Seiko Epson Co. |
 |
| Registration
for "JIEP Advanced Electronics Packaging(JISSO) Technology Symposium" |
| Please click here. Registation |
 |